Fishing – trapping – and vermin destroying
Patent
1994-11-23
1995-07-25
Fourson, George
Fishing, trapping, and vermin destroying
437 72, H01L 2176
Patent
active
054361907
ABSTRACT:
A method for fabricating a very narrow electrical isolation trench in a semiconductor substrate for isolating the individual field effect transistors (FETs) is achieved. This method eliminates the oxide encroachment into the device area associated with LOCOS techniques, thereby increasing device density. The method involves etching trenches, less than one half micrometer in width in the silicon substrate and forming sidewall spacer in the trench. The trench is filled with doped polysilicon and planarized, forming a trench which is planar with the device region. These isolation trenches are made in both N and P-wells for fabricating CMOS circuits having ULSI densities.
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"High Speed Bipolar ECL Devices Using a Vertical Isolated Self-Aligned Transistor" by T. Fujita et al, Japanese Journal of Applied Physics, vol. 22 (1983) Suppliment 22-1 pp. 125-128.
"Sensitivity of Field Isolation Profiles to Active Pattern" by P. U. Kenkane et al, IEDM, 1993, pub by IEEE pp. 479-481.
Wu Chung-Cheng
Yang Ming-Tzong
Fourson George
Saile George O.
United Microelectronics Corporation
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