Digital phase/frequency comparator

Details Digital phase/frequency comparator Digital phase/frequency comparator

1976-06-29

1977-06-21

Heyman, John S.

Registers

Coded record sensors

Particular sensor structure

235 92FQ, H03B 304

Patent

active

040314782

ABSTRACT:
Two D-type flip flops have a clock and a 1/4-bit delayed clock coupled to the D inputs of respective ones of the two flip flops to provide a +/- phase error of a present sample of digital data coupled to the clock inputs of the two flip flops and a second signal indicating a large/small phase error of the present sample of the data. A third signal indicating a +/- phase error of a previous state of the data is provided and a fourth signal indicating a large/small error of the previous state of the data is provided. A read only memory is responsive to the first, second, third and fourth signals in accordance with a given set of rules to produce a phase error signal with a clockwise change of phase states of the data providing a negative frequency error signal and a counter-clockwise change of phase states of the data providing a positive frequency error signal.

REFERENCES:
patent: 3922610 (1975-11-01), Buchan et al.
patent: 3989931 (1976-11-01), Phillips

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