Address buffer circuit for semiconductor memory

Details Address buffer circuit for semiconductor memory Address buffer circuit for semiconductor memory

1975-10-22

1977-06-21

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307DIG3, 307DIG4, 307DIG5, 340173R, H03K 3286, H03K 3353, G11C 1140, H03K 520

Patent

active

040314154

ABSTRACT:
Disclosed is an address buffer circuit for use in semiconductor memories or the like which are implemented in MOS integrated circuits. A cross-coupled differential pair of MOS transistors is used to detect an address input during a short time window, and internal address signals are generated from the state of the cross-coupled pair.

REFERENCES:
patent: 3678473 (1972-07-01), Wahlstrom
patent: 3796893 (1974-03-01), Hoffman et al.
patent: 3838404 (1974-09-01), Heeren
patent: 3848237 (1974-11-01), Geilhufe et al.
patent: 3902082 (1975-08-01), Proebsting et al.
patent: 3906464 (1975-09-01), Lattin
patent: 3909631 (1975-09-01), Kitagawa
patent: 3949381 (1976-04-01), Dennard et al.

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