Sense amplifier circuit using dummy memory cells

Details Sense amplifier circuit using dummy memory cells Sense amplifier circuit using dummy memory cells

1991-02-20

1992-09-15

Mullins, James B.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

365208, 365210, G11C 700

Patent

active

051480638

ABSTRACT:
A sense amplifier detects if a logic state of a detected memory cell transistor is "1" or "0" via a data line connected to the detected memory cell transistor. The sense amplifier includes a first dummy memory cell transistor which has characteristics identical to the "1" logic state characteristics of the detected memory cell transistor, a second dummy memory cell transistor which has characteristics identical to the "0" logic state characteristics of the detected memory cell transistor, and a differential amplifier circuit. The differential amplifier circuit receives signals from the data line and first and second reference lines respectively connected to the first and second dummy memory cell transistors, as a differential input, and outputs either a high or a low level according to the logic state of the detected memory cell based on the potential of the first or second reference line, the potential selected being that which differs from the potential of the data line.

REFERENCES:
patent: 4604732 (1986-08-01), Van Tran
Electronics, Information and Communication Institute, "High Speed Design Concept for Mask ROM", 1990.
The 1990 Symposium on VLSI Circuits, "A 36 ns 1Mbit CMOS EPROM with new data sensing technique," 1990.

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