Packet switching apparatus

Details Packet switching apparatus Packet switching apparatus

1993-09-03

1995-08-01

Safourek, Benedict V.

Multiplex communications

Wide area network

Packet switching

370 61, H04L 1256

Patent

active

054385679

ABSTRACT:
In the packet switching apparatus of the present invention, packets are inputted, parallel-expanded by a serial-parallel converter, multiplexed on a time division multiplexer, and address information of the packets is discriminated by address filters provided corresponding to the output ports. The address filters receive packets carrying relevant addresses and transmit them to corresponding buffers for storage. The buffers monitor the number of stored packets, and according to the results of comparison of the number of stored packets and buffer capacity, send control signals to reserve memory control assemblies to effect connection and disconnection between the reserve memories and the buffers. The stored packets are then sent from the buffers to the output ports.

REFERENCES:
patent: 5140583 (1992-08-01), May et al.
patent: 5204858 (1993-04-01), Kinashi et al.
patent: 5222064 (1993-06-01), Sagawa
Suzuki, H. et al, "Investigation of Converter Architecture for Asynchronous Transfer Mode", Technical Research Report SSE88-60, No. 128, Jul. 20, 1988 of the Institute of Electronics, Information, and Communication Engineers, pp. 61-66.
Suzuki, H., et al, "Output-Buffer Switch Architecture for Asynchronous Transfer Mode", International Journal of Digital and Analog Cabled Systems, vol. 2, 1989, pp. 269-276.
Kuwahara, H., et al, "A Shared Buffer Memory Switch for an ATM Exchange", IEEE, 1989, pp. 118-122.

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