System for flushing first and second caches upon detection of a

Details System for flushing first and second caches upon detection of a System for flushing first and second caches upon detection of a

1994-06-07

1995-04-18

Elmore, Reba I.

Boots, shoes, and leggings

3642434, 364964343, G06F 1312

Patent

active

054086361

ABSTRACT:
A computer system that flushes an internal cache in the microprocessor and an external cache to insure cache coherency. The computer system will flush the caches when a write command is directed to those specific portions that are write protected. The microprocessor is placed in a hold state before the flushing process is initiated. The cache memories are then cleared. Thus the microprocessor will not be able to read the incoherent information stored in the cache and yet data obtained during read operations can be cached for performance increase.

REFERENCES:
patent: 5210845 (1993-05-01), Crawford et al.
patent: 5325499 (1994-06-01), Kummer et al.
"i486 Processor Hardware Reference Manual", Intel Corporation, 1990, pp. 3-1-3-11 and 6-32-6-33.
"A Secondary Cache Controller Design for a High-End Microprocessor", Yong S. Lee, IEEE Journal, Nov. 11, 1991, pp. 1141-1146.
Microprocessors, vol. I, Intel, 1992; pp. 4-266 to 4-275.
Microprocessors, vol. I, Intel, 1992; pp. 2-80 to 2-81, 2-89 to 2-90.

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