Flash memory leveling architecture having no external latch

Details Flash memory leveling architecture having no external latch Flash memory leveling architecture having no external latch

1998-03-25

2000-03-21

Nelms, David

Static information storage and retrieval

Floating gate

Particular biasing

36518905, G11C 1134

Patent

active

060409975

ABSTRACT:
An improved flash memory system includes a flash array, internal buffer, and internal controller. When data is written from a source block to a destination block, the improved flash memory system temporarily holds this data inside the internal buffer within the flash memory system to save the overhead of sequentially transferring the data out of the flash system and then sequentially returning the data back to the system. Alternatively, the data can be read and concurrently programmed onto the destination block without being written into an internal latch. In use, this improved flash memory system simply transfers the data to be rewritten from the flash array either directly or to the internal buffer. This improved flash memory system locates a new address within this same flash array.

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