Translation of multiple virtual pages upon a TLB miss

Details Translation of multiple virtual pages upon a TLB miss Translation of multiple virtual pages upon a TLB miss

1990-05-24

1994-01-25

Dixon, Joseph L.

Boots, shoes, and leggings

395425, 364DIG1, 364DIG2, G06F 1200, G06F 1206, G06F 1210

Patent

active

052822745

ABSTRACT:
Apparatus, and accompanying methods for use therein, for translating virtual page addresses in one address space, e.g. virtual, to page addresses in a second address space, e.g. real, and specifically for increasing the speed of such translations by translating multiple contiguous virtual page addresses upon the occurrence of a miss in a translation lookaside buffer (TLB). In response to a TLB miss, the address of each virtual page in a pre-defined block of, e.g. four, contiguous virtual pages, is separately translated through segment and/or page table lookup operations to yield corresponding page frame addresses. The virtual and corresponding page frame addresses for this block are then stored within a single TLB entry. Inasmuch as successive virtual page addresses can be constructed through simple incrementation of a starting virtual page address for this block, a TLB entry contains the first virtual page address for the block followed by the separate page frame address, and its associated invalid and page protection bit fields, for each of the contiguous virtual pages in that block. Since segment and block values are the same for all the page frame addresses in each block, these values are only stored once within the corresponding TLB entry for that block.

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