Leading one anticipator and floating point addition/subtraction

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36471504, G06F 738

Patent

active

052821560

ABSTRACT:
A floating point addition/subtraction apparatus is internally provided with a leading one anticipator having redundant binary numeral generators, intermediate-carry/intermediate-sum generators, and scan-value generators. Each of the redundant binary numeral generators performs a subtraction with respect to two binary operands, a binary minuend and a binary subtrahend, to generate a redundant binary numeral Zsd having "-1", "0" or "1" at each digit thereof. Each of the intermediate-carry/intermediate-sum generators generates an intermediate carry C.sub.k and an intermediate sum S.sub.k in accordance with Zsd.sub.k =2C.sub.k +S.sub.k using a redundant binary numeral Zsd.sub.k positioned at a k.sup.th digit from a least significant digit of the redundant binary numeral Zsd and a redundant binary numeral Zsd.sub.k+1 positioned at a (k+1).sup.th digit so that C.sub.k =Zsd.sub.k when Zsd.sub.k+1 ="1" or "-1" and C.sub.k =0 when Zsd.sub.k+1 ="0". Each of the scan-value generators generates "1" (or "0") when a result of an addition with respect to an intermediate carry C.sub.k-1 and the intermediate sum S.sub.k is "0" and generates "0"(or "1") when the result of the addition is a numeral other than "0".

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patent: 4758974 (1988-07-01), Fields et al.
patent: 4785421 (1988-11-01), Takahashi
patent: 4864527 (1989-09-01), Peng et al.
patent: 4878192 (1989-10-01), Nishiyama et al.
patent: 4926369 (1990-05-01), Hokenek et al.

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