Pulse peak sample and hold circuit

Details Pulse peak sample and hold circuit Pulse peak sample and hold circuit

1976-02-23

1977-07-26

Zazworsky, John

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307353, 307358, 324103P, 328115, 328151, H03K 520

Patent

active

040385680

ABSTRACT:
A pulse peak sample and hold circuit includes a passive input integrator to develop the time of a sample gate. A sensitive comparator develops the gate pulse. A FET and storage capacitor "holds" the actual input amplitude. The circuit is independent of PRF and pulse width.

REFERENCES:
patent: 3723763 (1973-03-01), Udovic
patent: 3815026 (1974-06-01), Kraft et al.
patent: 3875516 (1975-04-01), Thomas

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