Multilayer ceramic multi-chip, dual in-line packaging assembly

Details Multilayer ceramic multi-chip, dual in-line packaging assembly Multilayer ceramic multi-chip, dual in-line packaging assembly

1975-05-12

1977-07-26

Smith, Jr., David

Electricity: conductors and insulators

Boxes and housings

Hermetic sealed envelope type

H05K 500

Patent

active

040384888

ABSTRACT:
A multilayer ceramic, multi-chip, dual in-line packaging assembly comprises a ceramic substrate with a pair of semiconductor chip receiving cavities therein. A metalization pattern partially embedded within the substrate provides electrical paths for semiconductor chip devices joined thereto to external circuitry. Semiconductor chips are joined to exposed pads within the chip receiving cavities. Metalization spaced from and positioned beneath the semiconductor chip devices completes interconnections between semiconductor chip devices. Exposed finger areas are spaced from one another and about the semiconductor chip receiving cavities. Embedded lines extend from the finger areas to external circuitry and interconnection means extend between finger areas. Finger areas on one side of a chip receiving cavity are offset with respect to the finger areas on the opposite side of the same chip receiving cavity but aligned with the finger areas on an adjacent chip receiving cavity to minimize crossover connections as well as the electrical coupling. An identical bonding design for each cavity also results. A lead frame is brazed to the substrate at its edges. A lid is bonded to the top surface of the substrate to hermetically seal chips within the chip receiving cavities thereby completing assembly of the package.

REFERENCES:
patent: 3549784 (1970-12-01), Hargis
patent: 3555364 (1971-01-01), Matcouich
patent: 3601522 (1971-08-01), Lynch
patent: 3617817 (1971-11-01), Kawakatsu et al.
patent: 3760090 (1973-09-01), Fowler

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