Process for fabricating a stacked capacitor having an I-shaped c

Details Process for fabricating a stacked capacitor having an I-shaped c Process for fabricating a stacked capacitor having an I-shaped c

1992-12-04

1994-01-25

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 60, 437919, H01L 2170, H01L 2700

Patent

active

052815498

ABSTRACT:
An existing stacked capacitor fabrication process is modified to construct a three-dimensional stacked capacitor, referred to as a Stacked I-Cell (SIC). The SIC design defines a capacitor storage cell that in the present invention is used in a DRAM process. The SIC is made up of a polysilicon storage node structure having a I-shaped cross-sectional upper portion with a lower portion extending downward and making contact to an active area via a buried contact. The polysilicon storage node structure is overlaid by polysilicon with a dielectric sandwiched in between to form a completed SIC capacitor. The novel 3-dimensional shaped polysilicon storage node plate having an adjustable I-shaped cross-section, allows substantial capacitor plate surface area of 200% or more to be gained at the storage node over that of a conventional STC.

REFERENCES:
patent: 4742018 (1988-05-01), Kimura et al.
patent: 5102820 (1992-04-01), Chiba
patent: 5108943 (1992-04-01), Sandhu et al.
patent: 5155057 (1992-10-01), Dennison et al.
"A Novel Storage Capacitance Enlargement Structure Using a Double-Stacked Storage Node in STC DRAM Cell", T. Kisu et al., Extended Abst of the 20th Conf. Solid State Device and Materials, Tokyo (1988), pp. 581-584.
"3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMS" by T. Ema et al., IEDM (1988), pp. 592-595.

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