Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1985-06-25

1987-06-23

Popek, Joseph A.

Static information storage and retrieval

Addressing

365189, G11C 800

Patent

active

046758500

ABSTRACT:
A semiconductor memory device is operable selectively in a page mode or a nibble mode, depending upon an external mode selection signal. In the page mode of operation a row address is supplied to the memory with subsequently supplied column addresses corresponding on a one-to-one basis with data to be stored into or read from memory. In the nibble mode of operation, the memory sequentially reads from or writes to four adjacent memory cells for each column address supplied.

REFERENCES:
patent: 4156938 (1979-05-01), Proebsting et al.
patent: 4344156 (1982-08-01), Eaton, Jr. et al.
patent: 4575825 (1986-03-01), Ozaki et al.
patent: 4586167 (1986-04-01), Fujishima et al.
IEEE Article by S. S. Eaton et al., "A 100 ns 64K Dynamic RAM using Redundancy Techniques", Technical Papers, pp. 84-85, Feb. 1981.

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