Semiconductor integrated circuit vertical geometry impedance ele

Details Semiconductor integrated circuit vertical geometry impedance ele Semiconductor integrated circuit vertical geometry impedance ele

1985-10-07

1987-06-23

James, Andrew J.

357 15, 357 43, 357 34, 357 67S, 357 71S, 357 2, H01L 2904

Patent

active

046757155

ABSTRACT:
A resistive load element comprises a Schottky barrier metal layer formed on the top surface of a doped p-type polycrystalline silicon (polysilicon) plug contacting a surface n.sup.+ zone located in a semiconductor body at a major horizontal surface thereof. The Schottky barrier metal layer is advantageously essentially a metal compound, such as titanium nitride, which does not react with the polysilicon and which forms a Schottky barrier contact with the polysilicon top surface of the plug. The polysilicon plug extends vertically down to the n.sup.+ zone through an aperture in an insulating layer that coats the major surface of the semiconductor body. The top surface of the Schottky barrier layer is coated with another metal layer, such as aluminum, for interconnection purposes. A pair of such elements can be integrated as loads, for example, in a static random access memory ("flip-flop") cell.

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