Method of making MOS read only memory by specified double implan

Details Method of making MOS read only memory by specified double implan Method of making MOS read only memory by specified double implan

1984-05-09

1985-10-29

Roy, Upendra

Metal working

Method of mechanical manufacture

Assembling or joining

29571, 148 15, 148187, 357 91, 357 2312, H01L 2978, H01L 21263

Patent

active

045493367

ABSTRACT:
The power consumption and corresponding speed of an integrated circuit is scaled by means of adjusting the channel width for MOS transistors. A transistor (12) is initially fabricated with a channel (24) having a width W.sub.1. The channel (24) receives a depletion type implant (30) to make the transistor (12) lightly depleted. An enhancement implant (32) is applied to the channel (24) to cover a selected area (24a). The enhancement implant (32) is made substantially stronger than the depletion implant (30). This results in a first section (24a) of the channel (24) having a large threshold voltage while the second section (24b) of channel (24) has a relatively small pinch-off voltage. The size of the second section (24b) is selectively controlled to scale the source-drain current of transistor (12) and the corresponding power consumption of the transistor (12). The method of applying the first and second implants (30, 32) can be easily incorporated into conventional ROM fabrication without the need for additional manufacturing steps.

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