Input buffer circuit for a microprocessor which prevents imprope

Details Input buffer circuit for a microprocessor which prevents imprope Input buffer circuit for a microprocessor which prevents imprope

1995-06-07

1996-07-23

Lim, Krisna

Boots, shoes, and leggings

395872, 364239, 3642397, 326 21, 326 56, G06F 1300, H03K 1900

Patent

active

055398871

ABSTRACT:
The present invention provides an input buffer circuit which prevents, when a microprocessor reads an external data bus upon bus sizing, a microprocessor from fetching an intermediate potential of the external data bus. READY terminal 3 is connected to one of a pair of input terminals of NOR gate 12 via latches 7 and 8, and lower data input terminal 4 is connected to the other input terminal of NOR gate 12. The output terminal of NOR gate 12 is connected to a data input terminal of data latch 14. SZRQ terminal 2 is connected to one of a pair of input terminals of NAND gate 10 via latches 5 and 6, and the output of latch 8 is connected to the other input terminal of NAND gate 10 via inverter 9. The output terminal of NAND gate 10 and upper data input terminal 1 are connected to input terminals of NOR gate 11, and the output terminal of NOR gate 11 is connected to an input terminal of data latch 13. Output terminals of data latches 13 and 14 serve as output terminals of the input buffer circuit.

REFERENCES:
patent: 4731553 (1988-03-01), Van Lehn et al.
patent: 4952367 (1990-08-01), Porter et al.
patent: 4954729 (1990-09-01), Urai
patent: 4961010 (1990-10-01), Davis
patent: 5038313 (1991-08-01), Kojima
patent: 5151621 (1992-09-01), Goto
patent: 5239214 (1993-08-01), Segawa et al.
patent: 5285117 (1994-02-01), Furutani
patent: 5285119 (1994-02-01), Takahashi

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