Method and circuitry for generating syndrome bits within an erro

Details Method and circuitry for generating syndrome bits within an erro Method and circuitry for generating syndrome bits within an erro

1992-10-05

1996-07-23

Baker, Stephen M.

Excavating

G06F 1110

Patent

active

055397549

ABSTRACT:
A method and circuit allows for generating syndrome bits from a plurality of data bits and a plurality of correction bits. The plurality of data bits are divided into subsets. From each subset of data bits, a plurality of syndrome bit partial products are generated using a logic gate tree, for example of XOR logic gates or XNOR logic gates. Each logic gate tree generates a syndrome bit partial product for each syndrome bit. The syndrome bits are generated from the syndrome bit partial products and from the correction bits, for example using XOR logic gates or XNOR logic gates. Within each logic gate tree, logic gates are arranged in rows. Each row of logic gates is used to generate a syndrome bit partial product for at least one syndrome bit.

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