Multiple length address formation in a microprogrammed data proc

Details Multiple length address formation in a microprogrammed data proc Multiple length address formation in a microprogrammed data proc

1978-01-10

1980-06-03

Nusbaum, Mark E.

Boots, shoes, and leggings

G06F 920

Patent

active

042065038

ABSTRACT:
A final effective address of an operand is generated in a microprogrammed data processing system by use of a base address register which may include an unindexed address, an index register which may include an indexed address value, an instruction register which may include an instruction word, which instruction word provides control over the addressing of a control store dependent upon the state of a selected one of a plurality of test conditions. One of the test conditions indicating whether some of the addressing values used in the generation of the effective address are in a short address format or in a long address format. The address control store word provides signals for controlling the operation of the system, including the branch in between such major operations as instruction fetching, addressing, reading, writing, and execution as well as branching between minor operations which are included in the major operations.

REFERENCES:
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patent: 3344404 (1967-09-01), Curewitz
patent: 3522589 (1970-08-01), Thron
patent: 3735355 (1973-05-01), Balogh, Jr. et al.
patent: 3949378 (1976-04-01), Crabb et al.
patent: 3972024 (1976-07-01), Schroeder et al.
patent: 4047247 (1977-09-01), Stanley et al.
Brown, W. W. et al., "Instructions for Byte Addressing Capability", IBM TDB, vol. 16, No. 3, Aug. 1973, pp. 812-815.

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