Memory programming load-line circuit with dual slope I-V curve

Details Memory programming load-line circuit with dual slope I-V curve Memory programming load-line circuit with dual slope I-V curve

1993-09-01

1995-03-14

LaRoche, Eugene R.

Static information storage and retrieval

Floating gate

Particular biasing

36518909, G11C 1134

Patent

active

053982037

ABSTRACT:
A non-volatile memory device is described. The memory device includes a memory array and current regulating circuitry coupled to the memory array. The memory array includes a first memory cell coupled to a first bit line and a second memory cell coupled to a second bit line such that the first memory cell receives a first current during programming of the first memory cell and the second memory cell receives a second current during programming of the second memory cell. The current regulating circuitry regulates the first and second currents during programming of the first and second memory cells such that when the first cell is being programmed and the second cell is not being programmed, the circuitry limits the first current flowing through the first bit line for programming the first memory cell to be substantially equivalent to the first current if the first and second memory cells are being programmed substantially at the same time. The current regulating circuitry allows the current-voltage characteristic of the programming load line to be controlled such that the characteristic, represented as a curve, may have two slopes and the shape and slopes of the curve may be adjusted independently.

REFERENCES:
patent: 4999813 (1991-03-01), Ohtsuka et al.
patent: 5245574 (1993-09-01), Frary et al.

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