Storage cell for nonvolatile electrically alterable memory

Static information storage and retrieval – Floating gate – Particular biasing

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G11C 1140

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044123116

ABSTRACT:
A storage cell of a nonvolatile electrically alterable MOS memory (EAROM) comprises a p-type silicon substrate with n-doped drain and source areas interlinked by an n-channel which is partly overlain by a floating gate extending over part of the drain area. An accessible gate overlaps the floating gate and has an extension overlying a gap between the latter gate and the source area to act as a common control electrode for two series IGFETs defined by the source and gate areas, namely a main or storage transistor and an ancillary or switching transistor. The capacitance of the floating gate relative to the drain area accounts for about half the overall capacitance of that gate relative to the entire semiconductor structure.

REFERENCES:
patent: 4087795 (1978-05-01), Rossler
patent: 4132904 (1979-01-01), Harari
patent: 4257056 (1981-03-01), Shum
patent: 4300212 (1981-11-01), Simko
IEEE Journal of Solid-State Circuits, vol. SC-14, No. 2, Apr. 1979, pp. 498-508, An Electrically Alterable, Nonvolatile Memory Cell Using a Floating-Gate Structure, Guterman et al.
IBM Technical Disclosure Bulletin, vol. 23, No. 1, Jun. 1980, pp. 227-228, Double Polysilicon Electrically Alterable Read-Only Structure Cell, Hsieh et al.

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