Boots – shoes – and leggings
Patent
1979-11-26
1983-10-25
Shaw, Gareth D.
Boots, shoes, and leggings
G06F 1516, G06F 1520
Patent
active
044123035
ABSTRACT:
A high speed parallel array data processing architecture fashioned under a computational envelope approach includes a data base memory for secondary storage of programs and data, and a plurality of memory modules interconnected to a plurality of processing modules by a connection network of the Omega gender. Programs and data are fed from the data base memory to the plurality of memory modules and from hence the programs are fed through the connection network to the array of processors (one copy of each program for each processor). Execution of the programs occur with the processors operating normally quite independently of each other in a multiprocessing fashion. For data dependent operations and other suitable operations, all processors are instructed to finish one given task or program branch before all are instructed to proceed in parallel processing fashion on the next instruction. Even when functioning in the parallel processing mode however, the processors are not locked-step but execute their own copy of the program individually unless or until another overall processor array synchronization instruction is issued.
REFERENCES:
patent: 3537074 (1970-10-01), Stokes et al.
patent: 4051551 (1977-09-01), Lawrie et al.
patent: 4101960 (1978-07-01), Stokes et al.
Concurrency: Single Processor Systems by Siewiork, Bell and Newell from Computer Structures (McGraw-Hill, Inc.), 1980.
Illiac IV System Proc. IEEE, Apr. 1972, pp. 369-388.
STARAN Proceedings Fall Joint Computer Conference 1972, pp. 229-241.
STARAN Proceedings National Computer Conference 1974, pp. 405-410.
C.mmp/Hydra Project-Carnegie Mellon University-1971.
Barnes George H.
Lundstrom Stephen F.
Shafer Philip E.
Brenner Leonard C.
Burroughs Corporation
Mills John G.
Peterson K. R.
Shaw Gareth D.
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