Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1995-12-19
1999-09-28
Dang, Trung
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438428, 438435, 438438, H01L 2176
Patent
active
059603003
ABSTRACT:
On a semiconductor substrate are successively deposited a silicon dioxide film and a silicon nitride film. The silicon nitride film, the silicon dioxide film, and the semiconductor substrate are sequentially etched using a photoresist film with an opening corresponding to an isolation region, thereby forming a trench. After depositing a diffusion preventing film, there is deposited an insulating film for isolation having reflowability. Although a void is formed in the insulating film for isolation in the isolation region, the insulating film for isolation is caused to reflow, thereby eliminating the void. After that, the whole substrate is planarized by CMP so as to remove the silicon nitride film and the silicon dioxide film, followed by the formation of gate insulating films, gate electrodes, sidewalls, and source/drain regions in respective element formation regions. Thus, in a highly integrated semiconductor device having a trench isolation, degradation of reliability resulting from the opening of the void in the surface of isolation is prevented.
REFERENCES:
patent: 4506435 (1985-03-01), Pliskin et al.
patent: 4571819 (1986-02-01), Rogers et al.
patent: 4740480 (1988-04-01), Ooka
patent: 4952524 (1990-08-01), Lee et al.
patent: 5433794 (1995-07-01), Fazan et al.
Nakabayashi Takashi
Segawa Mizuki
Uehara Takashi
Yabu Toshiki
Dang Trung
Matsushita Electric - Industrial Co., Ltd.
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