Method of fabricating a shallow-trench isolation structure in in

Details Method of fabricating a shallow-trench isolation structure in in Method of fabricating a shallow-trench isolation structure in in

1998-10-28

1999-09-28

Dang, Trung

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

438435, 438437, 438296, 148DIG50, H01L 2176

Patent

active

059602996

ABSTRACT:
A semiconductor fabrication method is provided for fabricating a shallow-trench isolation (STI) structure in an integrated circuit, which can prevent the occurrence of microscratches in the oxide plugs of the STI structure, thus further preventing the occurrence of a bridging effect and short-circuits between the circuit components that are intended to be electrically isolated by the STI structure. This method is characterized by the use of a laser annealing process to remove the microscratches that formed on the top surface of the oxide plugs during the chemical-mechanical polishing (CMP) process used to remove the upper part of the oxide layer to form the oxide plugs This method can therefore prevent the occurrence of a bridging effect and short-circuits due to the forming of the microscratches that would otherwise occur in the prior art.

REFERENCES:
patent: 5447884 (1995-09-01), Fahey et al.
patent: 5492858 (1996-02-01), Bose et al.
patent: 5763315 (1998-06-01), Benedict et al.
patent: 5786262 (1998-07-01), Jang et al.
patent: 5858858 (1999-01-01), Park et al.

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