1980-08-29
1983-10-25
Edlow, Martin H.
357 45, 357 41, H01L 2702
Patent
active
044122373
DESCRIPTION:
BRIEF SUMMARY
DESCRIPTION
Technical Field
The present invention relates to a semiconductor device and, more particularly, relates to a semiconductor device fabricated with a large number of large scale integrated CMIS (Complementary Metal Insulated Semiconductor) transistors, such as metal-oxide semiconductor transistors, arranged along both rows and columns of a semiconductor substrate.
Background Art
In recent years, a demand has arisen for fabrication of a large scale integrated semiconductor device which is suitable for low volume but wide variety manufacturing, without increasing the manufacturing cost and the manufacturing time. In response to this demand, the so-called masterslice semiconductor device has been proposed. In the masterslice semiconductor device, as is well known, first a large number of basic cells are formed on a single semiconductor substrate, however, no interconnecting lines formed therebetween or within each basic cell. Each of the basic cells is usually comprised of basic elements, such transistors, resistors and so on. A single semiconductor device comprised of only such basic cells is suitable for massproduction. After massproduction of the masterslice semiconductor device, the desired interconnecting lines between the basic cells and in each basic cell are then formed thereon by using a specified mask for wiring, in accordance with a variety of large scale integrated circuits to be fabricated for obtaining respective desired functional circuits.
In the masterslice semiconductor device, since the basic cells, each comprising transistors, resistors and so on are originally massproduced in the semiconductor substrate, a desired device can be completed by simply preparing a specified mask for forming the desired interconnecting lines every time a need for obtaining certain desired functional circuits occurs, and accordingly, a reduction of the manufacturing time can be achieved. Further, since the massproduced basic cells can be commonly utilized for obtaining any of the various kinds of functional circuits, a reduction of the manufacturing cost can be achieved. In addition, in the masterslice semiconductor device, since a large number of basic cells are regularly arranged along both rows and columns of the semiconductor substrate and form a standardized matrix pattern, it is very easy to employ the so-called computer aided automatic wiring operation for forming the interconnecting lines.
The above mentioned masterslice semiconductor device is disclosed, for example in the reports of the ISSCC 78/WEDNESDAY, Feb. 15, 1978/CONTINENTAL BALLROOM 4-5/4:15 PM and also ISSCC 78/WEDNESDAY, Feb. 15, 1978/CONTINENTAL BALLROOM 4-5/THAM 9.2. Generally, in the masterslice semiconductor device, there are several shortcomings. One shortcoming is that a high density of an integration can not be attained. This is because, each basic cell is isolated by spaces extending along rows and adjacent spaces extending along columns, and accordingly, the basic cells are scattered on the substrate. A second shortcoming is that interconnecting lines cannot be distributed uniformly on the substrate. This is because, firstly, the distribution of the interconnecting lines is carried out only in the spaces and, secondly, it is impossible to distribute the interconnecting lines on the basic cells, even if the cells are not to be used. Another shortcoming is that the densities of interconnecting lines at some portions of the spaces often become very high. This is because, each basic cell has only one input terminal electrode and one output terminal electrode. As mentioned above, a conventional masterslice semiconductor device lacks flexibility with regard to distribution of the interconnecting lines and, also, lacks capability of achieving a large integration of the basic cells.
DISCLOSURE OF INVENTION
An object of the present invention is, therefore, to provide a semiconductor device which has no shortcomings similar to the aforesaid shortcomings of the conventional masterslice semiconductor device, and accordingly,
REFERENCES:
patent: 4125854 (1978-11-01), McKenny
patent: 4128773 (1978-12-01), Troutman
patent: 4132904 (1979-01-01), Harari
patent: 4144561 (1979-03-01), Tu et al.
patent: 4148046 (1979-04-01), Hendrikson
patent: 4161662 (1979-07-01), Malcolm
Hoshikawa Ryusuke
Ichikawa Hiroaki
Matsumura Nobutake
Sato Syoji
Sugiura Yoshihide
Edlow Martin H.
Fujitsu Limited
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