Semiconductor device manufacturing: process – With measuring or testing
Patent
1997-10-31
1999-09-28
Niebling, John F.
Semiconductor device manufacturing: process
With measuring or testing
G01R 3126, H01L 2166
Patent
active
059602562
ABSTRACT:
A wafer layout for a multi-channel device for improving the yield of operative devices comprises a semiconductor wafer and a plurality of semiconductor devices formed in the semiconductor wafer, each device comprising a consecutive series of impurity regions formed in the semiconductor wafer, the impurity regions being arranged consecutively without separation between the respective semiconductor devices, such that each of the semiconductor devices is indistinguishable from the others, without regard to defective devices, and a single semiconductor device comprising a plurality of consecutive impurity regions formed in the semiconductor wafer may be cut from the wafer by cutting therefrom any of the plurality of consecutive impurity regions formed therein. The invention is particularly useful for the fabrication of strip diodes and the like.
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patent: 5559361 (1996-09-01), Pezzani
patent: 5561317 (1996-10-01), Momma et al.
Saito Yutaka
Sato Keiji
Niebling John F.
SII R&D Center Inc.
Zarneke David A.
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