Information processing section and system for operating a plural

Details Information processing section and system for operating a plural Information processing section and system for operating a plural

1995-03-27

1997-04-29

Bowler, Alyssa H.

Boots, shoes, and leggings

36423221, 3642329, 364DIG1, G06F 1576

Patent

active

056258348

ABSTRACT:
In an information processing system of the present invention, a vector processor has a plurality of vector pipeline sets operable under control of an instruction controller. The vector pipeline sets are operable in a parallel mode or in an individual mode with reference to an operation mode flag kept in a mode flag register. The instruction controller includes a plurality of vector instruction control units which correspond to the respective vector pipeline sets and which monitor states of the vector instruction control units to detect whether or not an error has taken place in each of the vector instruction control units. The vector pipeline sets are connected to a vector data memory through a pipeline crossbar switch to fetch a common data signal from the vector data memory on demand.

REFERENCES:
patent: 4777593 (1988-10-01), Yoshida
patent: 4803620 (1989-02-01), Inagami et al.
patent: 5239654 (1993-08-01), Ing-Simmons et al.
patent: 5261063 (1993-11-01), Kohn et al.
patent: 5355508 (1994-10-01), Kan
patent: 5475856 (1995-12-01), Kogge
"The OPSILA Computer", M. Augin et al., Parallel Algorithms & Architectures, Cosnard et al. (Editors), Apr. 1986, pp. 143-153.

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