Nested-loop-specialized circuitry for repeatedly performed arith

Details Nested-loop-specialized circuitry for repeatedly performed arith Nested-loop-specialized circuitry for repeatedly performed arith

1997-09-11

1999-09-28

An, Meng-Ai T.

39580023, 39580024, 39580033, 39580036, 395561, 395562, 395588, G06F 930

Patent

active

059602104

ABSTRACT:
An improved apparatus for processing a repeatedly performed arithmetic operation for a digital signal processor and a method thereof which are capable of pushing and popping values related to a repeat block to a register having a stack structure by providing a stack structure for processing a repeat block, this enabling a nested loop. The apparatus includes a register stack unit including a PASR register stack for pushing or popping a value to the PASR register, a PAER register stack for pushing or popping a value to the PAER register, and a BRCR register stack for pushing or popping a value to the BRCR register stack, a first comparison unit for judging whether a currently performed step is the end of the repeat block, and decreasing the value stored in the BRCR register by "1" when a desired condition is satisfied as a result of the judgement, otherwise, increasing the address value stored in the program counter by "1", and a second comparison unit for judging whether an externally inputted instruction corresponds to a state of the repeat block, outputting a control code based on the judged result to three stacks, respectively, and outputting the control code to the multiplexer in accordance with a control code from the first comparison unit, wherein said first comparison unit is enabled by receiving an externally inputted instruction through the second comparison unit.

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Texas Instruments "TMS320C2xx User's Guide", 1995, pp. 5-14.
Texas Instruments "TMS320C5x User's Guide", 1993, pp. 3-46 -3-50.

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