CMOS latch-up recovery circuit

Details CMOS latch-up recovery circuit CMOS latch-up recovery circuit

1986-11-20

1988-08-02

Pellinen, A. D.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Voltage regulator protective circuits

361 75, 361 86, 361 89, 363 21, 363 56, H02H 710

Patent

active

047617020

ABSTRACT:
An overcurrent shut down circuit for use in a switching regulator power supply comprised of circuitry for detecting the average current of a pulse width modulated input signal, comparing the average current with a predetermined threshold level and reducing the duty cycle of the pulse width modulated signal to zero thereby shutting off the power supply, in the event the detected current exceeds the threshold level, indicating excess current being drawn from an output circuit of the supply. Time delay circuitry is provided for resetting the shut down circuit and restoring the regulator to normal operation after a predetermined amount of time as elapsed subsequent to the power supply being shut down. The overcurrent shut down circuit provides for recovery from CMOS latch-up and other excess current drawing fault conditions without requiring that the power supply be manually turned off. The circuit is of straightforward and inexpensive design and occupies very little circuit board area.

REFERENCES:
patent: 4210947 (1980-07-01), Koizumi
patent: 4415960 (1983-11-01), Clark, Jr.
patent: 4646219 (1987-02-01), Rohl

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