Patent
1996-02-05
1997-04-29
Harrell, Robert B.
395598, G06F 930
Patent
active
056257864
ABSTRACT:
Other than a second bus selector to which first through fourth fields are entered with a 64-bit long MROM data bus divided into signals for each 16-bit field, a first bus selector to which the second and fourth fields are entered is provided. The bus selectors are simultaneously controlled by a bus selector/address controller so that a 16 or 32-bit external output terminal may generate a microinstruction word without altering the architecture of the circuit. Thus, it becomes possible to selectively generate the microinstruction word stored within the microprogram memory to external output terminals having different bit lengths.
REFERENCES:
patent: 4099229 (1978-07-01), Kancler
Kuban et al., "Testability Features of The MC68020" Internationl Test Conference (1984) pp. 821-827 (Paper 24.4).
Harrell Robert B.
NEC Corporation
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