Fishing – trapping – and vermin destroying
Patent
1993-06-14
1995-03-14
Chaudhuri, Olik
Fishing, trapping, and vermin destroying
437 60, 437919, 437200, H01L 2170, H01L 2700
Patent
active
053977297
ABSTRACT:
A method of fabricating a semiconductor device having a semiconductor substrate, a MOS transistor formed on one surface of the semiconductor substrate, and a capacitor is disclosed. The MOS has a gate electrode with a polycrystalline silicon layer and a metal silicide layer. The capacitor includes a first polycrystalline silicon layer which forms a lower electrode layer, an insulating interlayer, and a second polycrystalline silicon layer which forms an upper electrode, the first and second polycrystalline silicon layers sandwiching the insulating interlayer.
REFERENCES:
patent: 4208781 (1980-06-01), Rao et al.
patent: 4392299 (1983-07-01), Shaw
patent: 4577390 (1986-03-01), Haken
patent: 5025741 (1991-06-01), Suwanai et al.
Iki Koji
Kayanuma Sachiro
Asahi Kasei Microsystems Co. Ltd.
Chaudhuri Olik
Tsai H. Jey
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