Process for fabricating MOS transistors having full-overlap ligh

Fishing – trapping – and vermin destroying

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

437 29, 437 40, 437 41, H01L 21265

Patent

active

055389139

ABSTRACT:
A process for fabricating a MOS transistor having a full-overlap lightly-doped drain is disclosed. The MOS transistor is fabricated on a semiconductor silicon substrate that has formed thereon a field oxide layer that defines the active region of the MOS transistor. A field oxide layer is first used as the shielding mask for implanting impurities into the active region thereby forming a lightly-doped region. A shielding layer is then formed with an opening over the surface of the substrate. The opening has two sidewalls that generally define the channel region for the MOS transistor. A gate insulation layer is then formed over the surface of the substrate within the confinement of the opening. Conducting sidewall spacers are then formed over the sidewalls of the opening. The shielding layer and conducting sidewall spacers are then utilized as the shielding mask for implanting impurities into the lightly-doped region, thereby forming the channel region for the MOS transistor. A conducting layer is then formed over the surface of the gate insulation layer in the space as confined within the conducting sidewall spacers, wherein the conducting layer and the conducting sidewall spacers constitute the gate for the MOS transistor. The shielding layer is then removed. The gate and field oxide layer are used as the shielding mask for implanting impurities into the substrate, thereby forming a heavily-doped region, wherein the lightly-doped region completely overlaps the gate, and extends into the drain and source regions of the MOS transistor.

REFERENCES:
patent: 5082794 (1992-01-01), Pfiester et al.
patent: 5175119 (1992-12-01), Matsutani
patent: 5374574 (1994-12-01), Kwon
patent: 5374575 (1994-12-01), Kim et al.
patent: 5434093 (1995-07-01), Chau et al.
patent: 5489543 (1996-02-01), Hong

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Process for fabricating MOS transistors having full-overlap ligh does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for fabricating MOS transistors having full-overlap ligh, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for fabricating MOS transistors having full-overlap ligh will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-712666

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.