Semiconductor memory having a plurality of memory banks and sub-

Details Semiconductor memory having a plurality of memory banks and sub- Semiconductor memory having a plurality of memory banks and sub-

1996-02-23

1997-04-29

Nelms, David C.

Static information storage and retrieval

Read only systems

Semiconductive

36518516, 36518517, 36518513, G11C 1700

Patent

active

056255861

ABSTRACT:
In a semiconductor memory comprising one main bit line D1, a pair of main ground lines VG1 and VD2, a plurality of memory cell banks to be selectively connected to the main bit line D1 and the main ground lines VG1 and VD2, and a plurality of word lines W1 to Wn extending through the memory cell banks, each of the memory cell banks includes a plurality of wirings L1, L2, L3, L4 and L5 located in parallel to each other, and a threshold of a block selection transistor BT11 connected between the main bit line D1 and the wiring L3, is lower than that of block selection transistors BT12 and BT13 connected between the main bit line D1 and the wiring L2 and between the main bit line D1 and the wiring L4, respectively.

REFERENCES:
patent: 5040134 (1991-08-01), Park
patent: 5086413 (1992-02-01), Tsuboi et all
patent: 5345416 (1994-09-01), Nakagawara
patent: 5392233 (1995-02-01), Iwase

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