Method and apparatus for compacting integrated circuits with sta

Details Method and apparatus for compacting integrated circuits with sta Method and apparatus for compacting integrated circuits with sta

1994-09-27

1997-04-29

Teska, Kevin J.

Boots, shoes, and leggings

H01L 2198

Patent

active

056255683

ABSTRACT:
A computer-aided design system for compacting an integrated circuit layout with standard cell components is described. A data receiving device is used to process an integrated circuit layout that includes standard cell components. The integrated circuit layout is characterized by a circuit layout database with a cell table defining a set of cells that represent all spaces in the integrated circuit layout. The cell table includes connector cell data to indicate whether a cell forms a portion of a connected group of cells. The system includes an adjustment mechanism to align internal connectors of a standard cell with a routing grid associated with the integrated circuit layout. The system also includes a movement mechanism to position right-edge external connectors of a standard cell at a uniform routing grid coordinate position. The system uses the connector cell data to identify a power bus and a ground bus of each standard cell. Thereafter, a minimum edge to edge distance is assigned to each power bus and each ground bus. The connector cell data is also used to identify second metal plane routing paths. The system repositions selected second metal plane routing paths to increase routing path options.

REFERENCES:
patent: 4500963 (1985-02-01), Smith et al.
patent: 4577276 (1986-03-01), Dunlop et al.
patent: 4777606 (1988-10-01), Fournier
patent: 4815003 (1989-03-01), Putatunda et al.
patent: 5003256 (1991-03-01), Merrill
patent: 5191542 (1993-03-01), Murofushi
patent: 5235566 (1993-08-01), Merrill
patent: 5459673 (1995-10-01), Carmean et al.

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