Non-volatile semiconductor memory device

Static information storage and retrieval – Floating gate – Particular biasing

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Details

36518518, 36518533, G11C 1606

Patent

active

059598905

ABSTRACT:
A non-volatile semiconductor memory device comprises a bit line 402, a plurality of word lines 401 arranged to cross the bit line 402, a plurality of non-volatile memory cells 404 which are disposed at the crossing points of the bit line 402 and the word lines 401 and which have a drain 404a connected to the bit line 402 and a control gate 404f connected to the corresponding word line 401, and
a word line potential applying means 300, 500 wherein in an ordinary reading mode, a selective potential is applied to a word line 401 selected from the plurality of word lines, while a non-selective potential, which is lower than the selective potential, is applied to unselected word lines 401 in response to an address signal, and in a prescribed mode, the selective potential is applied to a word line 401 selected from the plurality of word lines, while a prescribed potential, which is lower than the non-selective potential, is applied to the unselected word lines in response to an address signal.

REFERENCES:
patent: 5602779 (1997-02-01), Gotou
patent: 5604711 (1997-02-01), Chueng
patent: 5636160 (1997-06-01), Omino et al.
patent: 5654920 (1997-08-01), Watsuji et al.
patent: 5654925 (1997-08-01), Koh et al.
patent: 5708606 (1998-01-01), Tanzawa et al.

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