Error correction processing scheme for sequential codec

Details Error correction processing scheme for sequential codec Error correction processing scheme for sequential codec

1985-05-23

1987-05-26

Atkinson, Charles E.

Excavating

G06F 1110

Patent

active

046690840

ABSTRACT:
A modified Fano signal processing scheme for a sequential codec defers a portion of path metric processing operations to a subsequent processing cycle by parallel branch metric processing. Rather than calculate and execute the effective path metric threshold changes in the same processing cycle, any threshold change that should result from the present processing cycle is fed forward to the branch metric calculation circuit so as to be readily available for use in the next processing cycle without having to be stored and subsequentially processed during the same processing cycle. The error correction/data recovery processor preferably employs a syndrome generator configured of a programmable read only memory which receives the bit stream to be processed and supplies impulse response bits to respective stages of a bidirectional shift register/exclusive-OR circuit. Also, the error correction processor is configured to accommodate multiple code rates through a common hardware arrangement which is implemented on the basis of a rate 3/4 code that makes it readily adaptable to both rate 1/2 and 7/8 codes.

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Lin et al., Error Control Coding-Fundamentals and Applications, Prentice-Hall, Inc., 1983, pp. 360-364.
Clark, Jr. et al., Error-Correction Coding for Digital Communications, Plenum Press, New York, 1981, pp. 297-330.

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