Method and apparatus in a data processor for selectively disabli

Details Method and apparatus in a data processor for selectively disabli Method and apparatus in a data processor for selectively disabli

1983-11-07

1987-05-26

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 900

Patent

active

046690590

ABSTRACT:
A method for allowing the user of a data processor having a power-down instruction to selectively disable the power-down instruction. In the preferred circuit, the user stores a special code in a control register indicating that the power-down instruction is to be disabled. Upon a power-down instruction being subsequently executed, the processor is precluded by the code from turning off the oscillator which provides the system clocks. The method and circuit allows the code to be stored in the control register once and only once between system resets.

REFERENCES:
patent: 3858182 (1974-12-01), Delagi et al.
patent: 4125867 (1978-11-01), Cochran
patent: 4245308 (1981-01-01), Hirschman
patent: 4290116 (1981-09-01), Morse
patent: 4316247 (1982-02-01), Iwamoto
patent: 4317181 (1982-02-01), Teza et al.
patent: 4409665 (1983-10-01), Tubbs
patent: 4463440 (1984-07-01), Nishiura et al.
patent: 4573117 (1986-02-01), Boney
patent: 4580246 (1986-04-01), Sibigtroth
Motorola: Single Chip Microcomputer Data, 2nd Printing, Motorola, Inc., 1984 pp. 3-891 to 3-894.

Affiliated with

Also associated with

Rating

Method and apparatus in a data processor for selectively disabli does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus in a data processor for selectively disabli, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus in a data processor for selectively disabli will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-708115