Synchronizing circuit

Details Synchronizing circuit Synchronizing circuit

1985-02-12

1987-05-26

Cardillo, Raymond F.

Dynamic magnetic information storage or retrieval

Converting an analog signal to digital form for recording;...

371 37, G11B 509, G06F 1110

Patent

active

046690000

DESCRIPTION:

BRIEF SUMMARY
DESCRIPTION

1. Technical Field
This invention relates to a synchronizing circuit for use with a PCM demodulating apparatus.
2. Background Art
In the prior art, an apparatus is proposed, in which a rotary head of, for example, a helical scan type is used. A recording tape is wrapped around a drum for the rotary head which has a wrap angle of 90.degree.. PCM data of an audio signal is timebase-compressed and then recorded on the recording tape during every period in which the rotary head comes in contact with the recording tape with an angular range of 90.degree..
In such apparatus, since the signal is compressed in timebase upon recording and reproduced intermittently upon playback, it is very difficult to establish accurate synchronization.
On the other hand, in a special playback mode such as a playback mode with a different reproducing speed, the reproduced data is thinned out so that it becomes more difficult to establish the synchronization.
Therefore, it was considered that together with a synchronizing signal, an address signal was added to a data signal for every block including a predetermined number of bits. According to this method, upon playback, the address signal is detected to enable accurate synchronization to be obtained.
In this case, however, the address signal requires a counter-measure such as an error correction and which must also be applied to the data signal. In that case, in the prior art, an error correction code is added commonly to both of the address signal and the data signal.
However, in this method, since the error correction code is added to the entire address and data signals, it is not possible to enhance the error correction ability by interleaving only the data signal. Alternatively, to carry out the interleaving, the address signal must be also stored and this requires a memory of a large capacity.
Further, in order to judge whether the address signal is correct or erroneous, the entire one block must be checked and this requires a memory for one entire block. Furthermore, there is a problem that even when the PCM data portion is correct, if the address portion is erroneous, the entire one block signal becomes erroneous.


DISCLOSURE OF INVENTION

In view of such problems, it is an object of this invention to provide a circuit of a simple construction capable of establishing accurate synchronization.


BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a diagram useful for explaining this invention and
FIG. 2 is a block diagram showing an embodiment of this invention.


BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1A shows a signal to be transmitted, in which the reference letter S designates a synchronizing signal. This synchronizing signal S is followed by an address signal A, error detection bits P for the address signal A, a data signal D and an error correction code C for the data signal D for a succeeding signal. This signal is transmitted sequentially. As the synchronizing signal, there is used an inhibited pattern or the like that does not exist inherently in the data signal.
FIG. 2 is a block diagram of a reproducing apparatus including the synchronizing circuit, in which the above-mentioned signal is supplied to an input terminal 1 as an RF signal that is modulated in, for example, NRZ-coding. This signal is supplied to a demodulating circuit 2 and demodulated to a code signal having levels of "1" and "0". This code signal is supplied to an error detecting circuit 3 for the address signal.
The RF signal from the input terminal 1 is also supplied to a synchronizing signal detecting circuit 4. In this case, since the above inhibited pattern or the like is employed, the synchronizing signal S can be directly detected from the RF signal as, for example, shown in FIG. 1B. This synchronizing signal S is supplied through an AND circuit 5 to the reset terminal of the detecting circuit 3. This detecting circuit 3 uses the address signal A and the error detecting bits P to judge whether the address signal is correct or erroneous and then produces a signal which becomes low le

REFERENCES:
patent: 4433348 (1984-02-01), Stockham, Jr. et al.
patent: 4433415 (1984-02-01), Kojima
patent: 4433416 (1984-02-01), Kojima
patent: 4499507 (1985-02-01), Yamada et al.
patent: 4525840 (1985-06-01), Heinz et al.

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