Reprogrammable instruction set accelerator using a plurality of

Details Reprogrammable instruction set accelerator using a plurality of Reprogrammable instruction set accelerator using a plurality of

1995-06-07

1998-05-05

Swann, Tod R.

395376, G06F 1576, G06F 930

Patent

active

057489793

ABSTRACT:
A microprocessor comprises a defined execution unit coupled to internal buses of the processor for execution of a predefined, fixed set of instructions, combined with one or more programmable execution units coupled to the internal buses for execution of a programmed instruction providing an on chip reprogrammable instruction set accelerator RISA. The programmable execution units may be made using a field programmable gate array having a configuration store, and resources for accessing the configuration store to program the programmable execution unit. An instruction register is included in the data processor which holds a current instruction for execution, and is coupled to an instruction data path to supply the instruction to the defined instruction unit and to the programmable instruction units in parallel, through appropriate decoding resources. A RISA instruction page table is used to detect when an instruction in the sequence has not been configured for the RISAs on chip. When a RISA instruction page table miss is detected, the program is stopped and programmable execution unit configured with the new instruction. Techniques for compiling a program using both RISA and fixed instructions optimizes utilization of configurable resources in the system. Further, synthesis of RISA instructions can be carried out on the fly during the execution of other instructions by the system, or this synthesis can be done at compile time.

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