Process for fabricating CMOS devices with self-aligned channel s

Details Process for fabricating CMOS devices with self-aligned channel s Process for fabricating CMOS devices with self-aligned channel s

1981-08-31

1983-10-25

Ozaki, G.

Metal working

Method of mechanical manufacture

Assembling or joining

29576B, 29578, 148187, 148190, H01L 21265

Patent

active

044110588

ABSTRACT:
An improved process is provided for fabricating CMOS (Complementary Metal Oxide Semiconductor) devices formed on a semiconductor substrate having n-channel and p-channel regions of n- and p-type conductivity, respectively. Conventional source, drain and gate portions are formed in the regions and electrical contacts are made thereto. The improvement comprises providing self-aligned channel stops between regions of the same conductivity and between regions of the opposite conductivity. The channel stops between regions of the opposite conductivity are mutually self-aligned. The self-alignment is achieved by use of a single mask, called a "complementary" mask. The process of the invention permits fabrication of submicrometer devices.

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