Processor microarchitecture for efficient processing of instruct

Details Processor microarchitecture for efficient processing of instruct Processor microarchitecture for efficient processing of instruct

1995-12-29

1998-11-03

Harrell, Robert B.

G06F 940

Patent

active

058322604

ABSTRACT:
A processor microarchitecture for efficient processing of instructions in a program including a program flow control instruction. The program flow control instruction specifies a target instruction and includes one or more candidate instructions between the target instruction and the program flow control instruction. A fetch unit fetches instructions in the program from the memory. Control logic stores one or more candidate instructions in the buffer prior to resolution of the conditional program flow control instruction in response to the fetch unit fetching a program flow control instruction specifying a target instruction within a predetermined number of instructions from the conditional program flow control instruction. In another embodiment, the candidate instructions are stored only if the conditional branch instruction is considered to be difficult to predict. The execution unit of the invention executes the candidate instructions if the conditional program flow control instruction is resolved to be not taken and ignores the candidate instructions, through no-ops in one embodiment, if the conditional program flow control instruction is resolved to be taken, thus avoiding a misprediction penalty.

REFERENCES:
patent: 5434985 (1995-07-01), Emma et al.
patent: 5511172 (1996-04-01), Kimura et al.
patent: 5634103 (1997-05-01), Dietz et al.
Gulati, et al.; "Performance Study of a Multithreaded Superscalar Microprocessor"; 1996 IEEE; pp. 291-301.
Popescu, et al.; "The Metaflow Architecture"; 1991 IEEE; pp. 10-13 and 63-73.
Chang, et al.; "The Importance of Prepass Code Scheduling for Superscalar and Superpipelined Processors"; 1995 IEEE; 353-370.
Pnevmatikatos, et al.; "Control Flow Prediction for Dynamic ILP Processors"; 1993 IEEE; pp. 153-163.
Uht, et al.; "Disjoint Eager Execution: An Optimal Form of Speculative Execution"; 1995 IEEE; pp. 313-325.
Pnevmatikatos, et al.; "Guarded Execution and Branch Prediction in Dynamic ILP Processors"; 21th International Symposium on Computer Architecture, 1994; 10 pages.
Mike Johnson; "Superscaler Microprocessor Design"; 1991 by Prentice-Hall, Inc., 288 pgs.

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