Method for isochronous flow control across an inter-chip bus

Details Method for isochronous flow control across an inter-chip bus Method for isochronous flow control across an inter-chip bus

1996-10-21

1998-11-03

An, Meng-Ai T.

395308, 395285, 395876, 395306, G06F 1337, G06F 1342

Patent

active

058322450

ABSTRACT:
A method for communicating data to a plurality of peripheral devices in a computer system, the computer system comprising a first bus, a bus bridge for coupling to the first bus and for interfacing to a second bus, a second bus coupled to the bus bridge, and a plurality of peripheral devices connected to the second bus. The method comprises activating a source port in the bus bridge to configure the source port in the bus bridge for a transfer. The bus bridge receives an address from the second bus. The bus bridge then stores the address in a register of the source port. The address identifies a destination port on a target peripheral device. The bus bridge then receives data from the first bus and stores the data in a buffer in the bus bridge. The bus bridge transmits one or more address/data pairs to the destination port. The address/data pairs each includes the address and data received from the first bus. The transmitting is performed in response to storing the data in a buffer in the bus bridge. The target peripheral device determines if the buffer in the bus bridge is substantially empty and transmits a flow control command requesting more data in response to determining that the buffer in the bus bridge is substantially empty. A receive port in the bus bridge receives the flow control command requesting more data from the target peripheral device. The bus bridge retrieves data from a memory in the computer system in response to the target peripheral device requesting more data and the receive port in the bus bridge receiving the request for more data from said target peripheral device. The data are stored in the buffer in the bus bridge. The bus bridge transmits one or more address/data pairs to the destination port of said target peripheral device, wherein the address/data pairs each includes the retrieved data.

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Peripheral Components, Intel, 1995, pp. ix, 1-1 through 1-72.

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