Computer system implementing a stop clock acknowledge special cy

Details Computer system implementing a stop clock acknowledge special cy Computer system implementing a stop clock acknowledge special cy

1996-12-31

1998-11-03

Ray, Gopal C.

Multiplex communications

Wide area network

Packet switching

395309, 39575004, 370402, G06F 1300, G06F 104

Patent

active

058322434

ABSTRACT:
A computer system using posted memory write buffers in a bridge can implement the stop clock acknowledge special cycle without faulty operation. The stop clock acknowledge transaction is posted in bridge buffers so that any previously posted memory write commands currently held in a posted memory write buffer in the bridge execute prior to the appearance of the posted stop clock acknowledge transaction. In this way, bridges having both posted write buffers and the stop clock special cycle may be utilized in efficient joint operation.

REFERENCES:
patent: 4545030 (1985-10-01), Kitchin
patent: 5519854 (1996-05-01), Watt
patent: 5555225 (1996-09-01), Hayashi et al.
patent: 5701503 (1997-12-01), Singh et al.

Affiliated with

Also associated with

Rating

Computer system implementing a stop clock acknowledge special cy does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Computer system implementing a stop clock acknowledge special cy, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Computer system implementing a stop clock acknowledge special cy will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-701265