Patent
1996-10-21
1998-11-03
An, Meng-Al T.
395309, G06F 1314
Patent
active
058322426
ABSTRACT:
A computer system, comprising a first expansion bus which operates according to a first transfer protocol. The first expansion bus is adapted to couple to one or more peripheral devices. A central processing unit and a bus bridge are operatively coupled to the first expansion bus. A second bus including a second transfer protocol is coupled to the bus bridge. A plurality of peripheral devices compatible with the second transfer protocol is coupled to the second bus. The bus bridge is configured to communicate with the plurality of peripheral devices in a round-robin ping-pong fashion. The bus bridge is configured to generate address/data pairs to at least one port of one of the peripheral devices, and thereafter receive address/data pairs from the one port of the peripheral device. The bus bridge is configured to generate and receive address/data pairs sequentially to ports in at least a subset of the plurality of peripheral devices in a round robin fashion.
REFERENCES:
patent: 5535341 (1996-07-01), Shah et al.
patent: 5649161 (1997-07-01), Andrade et al.
patent: 5659718 (1997-08-01), Osman et al.
patent: 5664117 (1997-09-01), Shah et al.
patent: 5694556 (1997-12-01), Neal et al.
PCI Local Bus Multimedia Design Guide, Revision 1.0, Mar. 29, 1994, pp. 1-40.
Peripheral Components, Intel, 1995, pp. ix, 1-1 through 1-72.
Advanced Micro Devices , Inc.
An Meng-Al T.
Dharia Rupal D.
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