Message transmission circuitry

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Details

371 32, G06F 1114

Patent

active

046213236

ABSTRACT:
The present invention provides parity error detection circuitry to effect an automatic second transmission of the data information signals in the event that a first transmission of said data information signals is determined to have a parity error. The invention includes a latch register through which data information signals are transmitted from a slave device to a master device and, there is also included parity check circuitry. When a parity error occurs in the transmission of data information signals, a parity error signal is generated by the master device which ultimately causes the latch register to hold the information which was previously transmitted as data signals and which data signals gave rise to the parity error. Accordingly a second set of data signals can be transmitted from the latch register, in an attempt to get a transmission of said data signals without error. The system also provides for detecting a parity error resulting from an irregular transmission of address information signals and such parity error gives rise to a parity error signal which acts in conjunction with logic circuitry to provide for a "retry" of the whole operation including a second transmission of the address signals and the data signals.

REFERENCES:
patent: 3824547 (1974-07-01), Green et al.
patent: 3979719 (1976-09-01), Tooley et al.

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