Patent
1994-01-10
1998-05-05
Harvey, Jack B.
39520007, 39520008, 395474, G06F 900
Patent
active
057489670
ABSTRACT:
In at least two microprocessor systems each having a microprocessor, a flash electrically erasable programmable read only memory (EEPROM), and a system bus connected to the microprocessor and the memory, there is disposed a controller between the system buses of the respective systems. The processor of one of the systems rewrites a program in the memory of a remaining system via the system bus of the remaining system.
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Nakamura Takahiro
Oka Takafumi
Harvey Jack B.
Hitachi , Ltd.
Seto Jeffrey K.
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