Memory device with staggered data paths

Details Memory device with staggered data paths Memory device with staggered data paths

1997-04-04

1998-11-03

Nelms, David C.

Static information storage and retrieval

Addressing

Sync/clocking

36518902, 36518905, 365194, 36523002, 36523008, G11C 700, G11C 800

Patent

active

058319298

ABSTRACT:
A memory device includes input and output data sequencers that transfer data between a memory array and a data bus where transfers between the data sequencers and the data bus are controlled by a first clock signal and transfers between a memory array and the data sequencers are controlled by a second clock signal of arbitrary phase relative to the first clock signal. Each data sequencer includes two or more sets of interim latches that each latch a portion of the data in a staggered fashion. One portion of the interim latches latch data while another portion transfers data to the data bus or the memory array. Because the data is segmented into portions and each portion is activated separately, the data can be transferred quickly without data collisions.

REFERENCES:
patent: 5513327 (1996-04-01), Farmwald et al.
patent: 5655105 (1997-08-01), McLaury

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