Method for controlling erasure of nonvolatile semiconductor memo

Details Method for controlling erasure of nonvolatile semiconductor memo Method for controlling erasure of nonvolatile semiconductor memo

1997-03-17

1998-11-03

Nguyen, Viet Q.

Static information storage and retrieval

Floating gate

Particular biasing

365218, 36518524, 36518522, G11C 1606

Patent

active

058319050

ABSTRACT:
The present invention has a structure wherein a word line erasing voltage is inhibited from being applied to a sector (each word line) in which it is decided that erasure has been completed. Consequently, a method for controlling erasure of a nonvolatile semiconductor memory is provided in which distribution of a threshold can be tight without increasing a layout area so that a threshold of a reference cell for erasure can be lowered, read can be performed without boosting the word line by using a power supply having a low voltage, and high-speed read and low power consumption can thus be realized.

REFERENCES:
patent: 5239505 (1993-08-01), Fazio et al.
patent: 5526309 (1996-06-01), Jinho
patent: 5537358 (1996-07-01), Fong
patent: 5581503 (1996-12-01), Matsubara et al.

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