Non-volatile semiconductor memory device capable of conditioning

Details Non-volatile semiconductor memory device capable of conditioning Non-volatile semiconductor memory device capable of conditioning

1996-08-01

1998-11-03

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

36518509, 36518513, 3651853, 36518533, G11C 1606

Patent

active

058319042

ABSTRACT:
By setting full group reversal control gates to a logical voltage "H", memory cells on all bit lines of a memory cell array block are connected to a reversal voltage supply circuit so that a group reversal operation is performed. When one of the group reversal control gates is set to the logical voltage "H", the memory cells on the bit lines having either even or odd numbers of the memory cell array block are connected to the reversal voltage supply circuit so that a partial group reversal operation is performed. When one of column selection gates is set to the logical voltage "H", the selected bit line is connected to the reversal voltage supply circuit. Consequently, a line reversal operation for the memory cell connected to the selected bit line is performed. Thus, the high-speed reversal operation which fully controls the offleak current of the memory cell can be implemented and the low-voltage operation can be realized by changing the operation unit for performing the reversal operation.

REFERENCES:
patent: 5546340 (1996-08-01), Hu et al.
patent: 5568419 (1996-10-01), Atsumi et al.
patent: 5576991 (1996-11-01), Radjy et al.
patent: 5608672 (1997-03-01), Tang et al.

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