Microprocessor having delayed instructions

Details Microprocessor having delayed instructions Microprocessor having delayed instructions

1997-01-27

1998-09-29

Harrell, Robert B.

G06F 934

Patent

active

058156984

ABSTRACT:
A microprocessor executes delayed instructions in which decoded results obtained at the instruction decoder unit 2 are stored in the ALU 361, the multiplier 363, the PC controller 365, the memory controller 367, and the shifter 369, and a program counter value related to a delayed value specified by a delayed instruction is stored into registers 362B, 364B, 366B and 370B.

REFERENCES:
patent: 4926323 (1990-05-01), Barer et al.
patent: 5305446 (1994-04-01), Leach et al.
patent: 5535348 (1996-07-01), Leach et al.
"Optimizing Delayed Branches", Gross et al., Departments of Electrical Engineering and Computer Science, Stanford University, 0194-1895/82/0000/014 1982 IEEE, pp. 114-120.
"Reducing the Cost of Branches", McFarling et al., Computer Systems Laboratory, Stanford University, 0884-7495/86/0000/0396, 1986 IEEE, pp. 396-403.
Computer Architecture A Quantitative Approach, Hennessy et al., "The Major Hurdle of Pipelining-Pipeline Hazards", pp. 272-278.

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