Semiconductor integrated circuit equipped with test circuit

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39518319, G01R 3128

Patent

active

058155112

ABSTRACT:
An integrated circuit device equipped with a test circuit includes a plurality of input/output terminals, an input terminal, and an internal circuit for receiving input data via the plurality of input/output terminals and outputting output data. The test circuit permits data exchange among the input/output terminals, the input terminal and the internal circuit. The test circuit preferably operates in a normal mode to supply input data to the internal circuit through the input/output terminals, and supply output data from the internal circuit through the input/output terminals. The test circuit further operates in a test mode to supply test input data to the internal circuit through one of the input terminal and the input/output terminals. The test circuit further supplies test output data that is output from the internal circuit to one of the input terminal and the input/output terminals which differ from the test input data supplied terminal.

REFERENCES:
patent: 5166937 (1992-11-01), Blecha, Jr.
patent: 5225774 (1993-07-01), Imamura
patent: 5369646 (1994-11-01), Shikatani
patent: 5457381 (1995-10-01), Farwell
patent: 5615216 (1997-03-01), Saeki
patent: 5648973 (1997-07-01), Mote, Jr.
patent: 5656953 (1997-08-01), Whetsel

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